1. Field of the Invention
The present invention relates to an operation mode setting system for a microprocessor in which various operation modes are set in multi-valued logic by the use of analog signals.
2. Description of the Prior Art
As microprocessors have progressed, their applications have widened, and systems employing microprocessors have come to have multifarious variations. That is, if it is desired to change, e.g., I/O characteristics, memory maps or the polarities of certain signal lines are changed through simple modifications while fundamental functions are maintained.
On the other hand, it is favorable from the point of view of the reliability and cost of a device itself to mass-produce the IC, especially an LSI such as is used in a microprocessor, by the use of the same mask pattern. Therefore, fundamentally the following three techniques are used at present in order to accomodate the user's extended needs as mentioned above:
(1) Only specified ones of masks are partly and simply modified to meet the desired variations (the so-called master slice method).
(2) External devices are selected for a system by the user. In some cases, such external devices are separately prepared as peripheral devices by the manufacturer.
(3) Several pins of a device are used for assigning specific operation modes, and the device is instructed to start the several operation modes through inputs to the pins.
Microprocessors presently available are constructed so that they can operate in various operation modes, for example, a test mode and a user mode or they can exchange a plurality of kinds of memory maps. These modes are externally set in the two-valued logic through the pins of an integrated circuit chip which forms the microprocessor. The number of the pins for setting the operation modes is, however, limited because a large number of pins are required for allowing the microprocessor to perform functions other than operation mode setting. For this reason, increases in the number of the pins for setting operation modes have been stopped. However, the expedient has still been unsatisfactory, particularly when a comparatively large number of operation modes need to be set.
More specifically, referring back to the aforementioned techniques, the method (1) results in preparing the masks individually. This is undesirable because a certain degree of mass-production is necessary. Moreover, the functions which can be changed by the specified masks are still limited. With the method (2), the user requires the peripheral devices. This poses problems in cost and in reliability. The method (3) is considered to be the best. It incurs no problem when the IC has surplus pins, but the number of pins is usually limited.
There will now be described a prior-art system wherein operation modes are determined by the two-valued logic.
An I/O port register built in a microprocessor is shown in FIG. 1A by way of example. It is assumed that the three upper bits of bits 7, 6 and 5 are used for setting the operation modes. An example of an external circuit in the case of the bus separable extension mode is shown in FIG. 1B. The logical values of pins 10, 9 and 8 are respectively stored in the bits 7, and 5 of the I/O port register. Thus, the operation modes are set.
In the reset status, the pins 10, 9 and 8 of the microprocessor are respectively programmed at "1", "0" and "1" as illustrated in FIG. 1B. In a case where the pins 8-10 are wired to a peripheral circuit and where at the turn-on of a power supply, the peripheral circuit requires signals different from the signals necessary for the mode programming, a switch is needed as shown in FIG. 1B and a circuit shown in FIG. 1C is used for separating the peripheral circuit and the microprocessor during the reset period.
The operation modes after the resetting must be determined in such a way that the user wires the pins 10, 9 and 8 as external hardware. The signals of the three pins are latched in the program control bits PC2, PC1 and PC0 of the I/O port register in FIG. 1A when the reset signal switches to the "1" level.
The circuit of FIG. 1B can be operated in various modes by latching the values of the pins 8, 9 and 10 at the leading edge of a RESET signal.
By way of example, in the case where the processor has four I/O ports 1, 2, 3 and 4, the following modes are possible. All the ports function as I/O ports (single chip mode). The ports 1 and 2 function as I/O ports, the port 3 as a data bus, and the port 4 as a lower bit address bus or a part thereof (bus separable extension mode). The ports 1 and 2 function as I/O ports, the port 3 receives and delivers a lower bit address and data in a time-sharing fashion, and the port 4 delivers an upper bit address (bus time-sharing extension mode). In this mode, the address space of a memory can be enlarged. Thus, the largest utilizable address space is achieved in the bus time-sharing extension mode.
In this manner, the prior art sets operation modes in the two-valued logic by means of an external circuit, which leads to the disadvantage of a large number of pins.
A method for reducing the number of pins for setting operation modes is to use input/output pins in common. In this case, however, the pins must be partitioned in accordance with the change-over of the operation modes. The partitioning inevitably results in the drawback that the input/output electrical characteristics of the mode input pin circuitry changes.